? semiconductor components industries, llc, 2011 november, 2011 ? rev. 4 1 publication order number: nlsv4t240e/d nlsv4t240e 4-bit dual-supply inverting level translator the nlsv4t240e is a 4 ? bit configurable dual ? supply voltage level translator. the input a n and output b n ports are designed to track two different power supply rails, v cca and v ccb respectively. both supply rails are configurable from 0.9 v to 4.5 v allowing universal low ? voltage translation from the input a n to the output b n port. the nlsv4t240e is similar to the nlsv4t240; however, it has enhanced power ? off characteristics. features ? wide v cca and v ccb operating range: 0.9 v to 4.5 v ? high ? speed w/ balanced propagation delay ? inputs and outputs have ovt protection to 4.5 v ? non ? preferential v cca and v ccb sequencing ? outputs at 3 ? state until active v cc is reached ? power ? off protection ? outputs switch to 3 ? state with v ccb at gnd ? ultra ? small packaging: 1.7 mm x 2.0 mm uqfn12 ? this is a pb ? free device typical applications ? mobile phones, pdas, other portable devices important information ? esd protection for all pins: hbm (human body model) > 6000 v mm (machine model) > 300 v uqfn12 mu suffix case 523ae marking diagrams http://onsemi.com aem 1 device package shipping ? ordering information nlsv4t240emutag uqfn12 (pb ? free) 3000/tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. NLSV4T240EDR2G so ? 14 (pb ? free) 2500/tape & reel nlsv4t240edtr2g tssop14 (pb ? free) 2500/tape & reel soic ? 14 d suffix case 751a 14 1 4t240eg awlyww 1 14 tssop ? 14 dt suffix case 948g 14 1 sv4t 240e alyw 1 14 a = assembly location l, wl = wafer lot y, yy = year w, ww = work week g or = pb ? free package (note: microdot may be in either location) ae = specific device code m = date code = pb ? free package (note: microdot may be in either location)
nlsv4t240e http://onsemi.com 2 figure 1. pin assignments 13 14 12 11 10 9 8 2 1 34567 oe v ccb b1 b2 b3 nc b4 v cca a1 a2 a3 a4 nc gnd 1 2 3 4 5 11 10 9 8 7 12 6 (top view) a1 a2 a3 a4 v ccb b1 b2 b3 b4 v cca oe gnd figure 2. logic diagram v cca v ccb b1 b2 a2 a1 b3 b4 oe a4 a3 pin assignment pin function v cca input port dc power supply v ccb output port dc power supply gnd ground a n input port b n output port oe output enable inputs outputs oe a n b n truth table llh lhl hx3 ? state
nlsv4t240e http://onsemi.com 3 maximum ratings symbol rating value condition unit v cca , v ccb dc supply voltage ? 0.5 to +5.5 v v i dc input voltage a n ? 0.5 to +5.5 v v c control input oe ? 0.5 to +5.5 v v o dc output voltage (power down) b n ? 0.5 to +5.5 v cca = v ccb = 0 v (active mode) b n ? 0.5 to +5.5 v (tri ? state mode) b n ? 0.5 to +5.5 v i ik dc input diode current ? 20 v i < gnd ma i ok dc output diode current ? 50 v o < gnd ma i o dc output source/sink current 50 ma i cca , i ccb dc supply current per supply pin 100 ma i gnd dc ground current per ground pin 100 ma t stg storage temperature ? 65 to +150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. recommended operating conditions symbol parameter min max unit v cca , v ccb positive dc supply voltage 0.9 4.5 v v i bus input voltage gnd 4.5 v v c control input oe gnd 4.5 v v io bus output voltage (power down mode) b n gnd 4.5 v (active mode) b n gnd v ccb v (tri ? state mode) b n gnd 4.5 v t a operating temperature range ? 40 +85 c t / v input transition rise or rate v i , from 30% to 70% of v cc ; v cc = 3.3 v 0.3 v 0 10 ns dc electrical characteristics symbol parameter test conditions v cca (v) v ccb (v) ? 40 c to +85 c unit min max v ih input high voltage (an, oe ) 3.6 ? 4.5 0.9 ? 4.5 2.7 ? v 2.7 ? 3.6 2.0 ? 2.3 ? 2.7 1.7 ? 1.4 ? 2.3 0.75 * v cca ? 0.9 ? 1.4 0.9 * v cca ? v il input low voltage (an, oe ) 3.6 ? 4.5 0.9 ? 4.5 ? 0.8 v 2.7 ? 3.6 ? 0.8 2.3 ? 2.7 ? 0.7 1.4 ? 2.3 ? 0.35 * v cca 0.9 ? 1.4 ? 0.1 * v cca
nlsv4t240e http://onsemi.com 4 dc electrical characteristics symbol unit ? 40 c to +85 c v ccb (v) v cca (v) test conditions parameter symbol unit max min v ccb (v) v cca (v) test conditions parameter v oh output high voltage i oh = ? 100 a; v i = v ih 0.9 ? 4.5 0.9 ? 4.5 v ccb ? 0.2 ? v i oh = ? 0.5 ma; v i = v ih 0.9 0.9 0.75 * v ccb ? i oh = ? 2 ma; v i = v ih 1.4 1.4 1.05 ? i oh = ? 6 ma; v i = v ih 1.65 1.65 1.25 ? 2.3 2.3 2.0 ? i oh = ? 12 ma; v i = v ih 2.3 2.3 1.8 ? 2.7 2.7 2.2 ? i oh = ? 18 ma; v i = v ih 2.3 2.3 1.7 ? 3.0 3.0 2.4 ? i oh = ? 24 ma; v i = v ih 3.0 3.0 2.2 ? v ol output low voltage i ol = 100 a; v i = v il 0.9 ? 4.5 0.9 ? 4.5 ? 0.2 v i ol = 0.5 ma; v i = v ih 1.1 1.1 ? 0.3 i ol = 2 ma; v i = v ih 1.4 1.4 ? 0.35 i ol = 6 ma; v i = v il 1.65 1.65 ? 0.3 i ol = 12 ma; v i = v il 2.3 2.3 ? 0.4 2.7 2.7 ? 0.4 i ol = 18 ma; v i = v il 2.3 2.3 ? 0.6 3.0 3.0 ? 0.4 i ol = 24 ma; v i = v il 3.0 3.0 ? 0.55 i i input leakage current v i = v cca or gnd 0.9 ? 4.5 0.9 ? 4.5 ? 1.0 1.0 a i off power ? off leakage current oe = 0 v 0 0.9 ? 4.5 0.9 ? 4.5 0 ? 1.0 ? 1.0 1.0 1.0 a i cca quiescent supply current v i = v cca or gnd; i o = 0, v cca = v ccb 0.9 ? 4.5 0.9 ? 4.5 ? 2.0 a i ccb quiescent supply current v i = v cca or gnd; i o = 0, v cca = v ccb 0.9 ? 4.5 0.9 ? 4.5 ? 2.0 a i cca + i ccb quiescent supply current v i = v cca or gnd; i o = 0, v cca = v ccb 0.9 ? 4.5 0.9 ? 4.5 ? 4.0 a i cca increase in i cc per input voltage, other inputs at v cca or gnd v i = v cca ? 0.6 v; v i = v cca or gnd 4.5 3.6 4.5 3.6 ? 10 5.0 a i ccb increase in i cc per input voltage, other inputs at v cca or gnd v i = v cca ? 0.6 v; v i = v cca or gnd 4.5 3.6 4.5 3.6 ? 10 5.0 a i oz i/o tri ? state output leakage current (t a = 25 c, oe = v cca ) v o = 0 v 4.5 4.5 ? 1.0 a v o = 4.5 v 4.5 4.5 ? 10 v o = 0 to 4.5 v 2.5 3.5 ? 105 3.0 3.75 ? 110 3.3 3.0 ? 75 3.75 1.5 ? 10
nlsv4t240e http://onsemi.com 5 total static power consumption (i cca + i ccb ) ? 40 c to +85 c v ccb (v) 4.5 3.3 2.8 1.8 0.9 v cca (v) min max min max min max min max min max unit 4.5 2 2 2 2 < 1.5 a 3.3 2 2 2 2 < 1.5 a 2.8 < 2 < 1 < 1 < 0.5 < 0.5 a 1.8 < 1 < 1 < 0.5 < 0.5 < 0.5 a 0.9 < 0.5 < 0.5 < 0.5 < 0.5 < 0.5 a note: connect ground before applying supply voltage v cca or v ccb . this device is designed with the feature that the power ? up sequence of v cca and v ccb will not damage the ic. ac electrical characteristics symbol parameter v cca (v) ? 40 c to +85 c unit v ccb (v) 4.5 3.3 2.8 1.8 1.5 min max min max min max min max min max t plh , t phl (note 1) propagation delay, a n to b n 4.5 3.0 3.2 3.4 3.7 4.0 ns 3.6 3.3 3.5 3.7 4.0 4.3 2.8 3.5 3.7 3.9 4.2 4.5 1.8 3.8 4.0 4.2 4.5 4.8 1.5 4.1 4.3 4.5 4.8 5.0 t pzh , t pzl (note 1) output enable, oe to b n 4.5 4.4 4.8 5.2 5.7 6.2 ns 3.3 4.7 5.1 5.5 6.0 6.5 2.8 4.9 5.3 5.7 6.2 6.7 1.8 5.2 5.6 6.0 6.5 7.0 1.5 5.5 5.9 6.3 6.8 7.3 t phz , t plz (note 1) output disable, oe to b n 4.5 4.4 4.8 5.2 5.7 6.2 ns 3.3 4.7 5.1 5.5 6.0 6.5 2.8 4.9 5.3 5.7 6.2 6.7 1.8 5.2 5.6 6.0 6.5 7.0 1.5 5.5 5.9 6.3 6.8 7.3 t oshl , t oslh (note 1) output to output skew, data to out- put 4.1 0.15 0.15 0.15 0.15 0.15 ns 3.6 0.15 0.15 0.15 0.15 0.15 2.8 0.15 0.15 0.15 0.15 0.15 1.8 0.15 0.15 0.15 0.15 0.15 1.2 0.15 0.15 0.15 0.15 0.15 1. propagation delays defined per figures 3 and 4. capacitance symbol parameter test conditions typ (note 2) unit c in control pin input capacitance v cca = v ccb = 3.3 v, v i = 0 v or v cca/b 3.5 pf c i/o i/o pin input capacitance v cca = v ccb = 3.3 v, v i = 0 v or v cca/b 5.0 pf c pd power dissipation capacitance v cca = v ccb = 3.3 v, v i = 0 v or v cca , f = 10 mhz 20 pf 2. typical values are at t a = +25 c. 3. c pd is defined as the value of the ic?s equivalent capacitance from which the operating current can be calculated from: i cc(operating) c pd x v cc x f in x n sw where i cc = i cca + i ccb and n sw = total number of outputs switching.
nlsv4t240e http://onsemi.com 6 figure 3. ac (propagation delay) test circuit dut pulse generator v cc c l r l r l v cco x 2 open gnd test switch t plh , t phl open t plz , t pzl v cco x 2 t phz , t pzh gnd c l = 15 pf or equivalent (includes probe and jig capacitance) r l = 2 k or equivalent z out of pulse generator = 50 figure 4. ac (propagation delay) test circuit waveforms input (a n ) output (b n ) oe n vm vm vm vm vm vm vm vm t plh t phl v ih 0 v v oh v ol v ih 0 v v oh v y v ol v x t pzh t pzl t phz t plz 0 v v cc waveform 1 ? propagation delays t r = t f = 2.0 ns, 10% to 90%; f = 1 mhz; t w = 500 ns waveform 2 ? output enable and disable times t r = t f = 2.0 ns, 10% to 90%; f = 1 mhz; t w = 500 ns output (b n ) output (b n ) symbol v cc 3.0 v ? 4.5 v 2.3 v ? 2.7 v 1.65 v ? 1.95 v 1.4 v ? 1.6 v 0.9 v ? 1.3 v v ma v cca /2 v cca /2 v cca /2 v cca /2 v cca /2 v mb v ccb /2 v ccb /2 v ccb /2 v ccb /2 v ccb /2 v x v ol x 0.1 v ol x 0.1 v ol x 0.1 v ol x 0.1 v ol x 0.1 v y v oh x 0.9 v oh x 0.9 v oh x 0.9 v oh x 0.9 v oh x 0.9
nlsv4t240e http://onsemi.com 7 applications information figure 5. typical tri ? state output (c l = 50 pf, r l = 2 k , r pull ? up = 50 k , test circuit shown in figure 3) figure 6. typical tri ? state output (c l = 50 pf, r l = , r pull ? up = 2 k , test circuit shown in figure 3) typical tri ? state output waveforms of the nlsx4t240e are shown in figures 5 and 6. the shape of the output waveform during a tri ? state condition corresponding to the disable time (t phz , t plz ) depends on the configuration of the pull ? up circuit. figure 5 shows a smooth monotonically increasing exponentially waveform because a 2 k resistance is connected between the output and ground. figure 6 shows that the output may have a ?shelf? or a short duration where the slope of the waveform is equal to zero if no load resistance is connected to ground. the nlsx4t240e was created from the nlsx4t240 to minimize the ?shelf? of the waveform during the disable time.
nlsv4t240e http://onsemi.com 8 package dimensions uqfn12 1.7x2.0, 0.4p case 523ae ? 01 issue a a b a1 0.05 c seating plane note 3 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal tip. 4. mold flash allowed on terminals along edge of package. flash 0.03 max on bottom surface of terminals. 5. detail a shows optional construction for terminals. dim min max millimeters a a1 0.40 bsc 0.45 0.55 b d 0.45 0.55 e e l 0.00 0.05 pin 1 reference d a e b 0.10 c 2x 0.10 c 2x 0.05 c c k 7 5 1 11 12x e l 12x 2.00 bsc 0.15 0.25 12x a3 detail b 8x l2 detail b optional construction 0.15 ref l2 k 0.127 ref a3 1.70 bsc top view side view bottom view note 5 l1 detail a detail a b a c c m 0.10 m 0.05 0.32 11x 2.30 0.69 0.40 dimensions: millimeters mounting footprint 1 soldermask defined 0.00 0.03 l1 0.22 2.00 pitch 12x 0.20 ---- *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
nlsv4t240e http://onsemi.com 9 package dimensions soic ? 14 d suffix case 751a ? 03 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. ? a ? ? b ? g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t ? t ? f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019 7.04 14x 0.58 14x 1.52 1.27 dimensions: millimeters 1 pitch soldering footprint 7x
nlsv4t240e http://onsemi.com 10 package dimensions tssop ? 14 dt suffix case 948g ? 01 issue b dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l ? u ? seating plane 0.10 (0.004) ? t ? ??? ??? section n ? n detail e j j1 k k1 ? w ? 0.25 (0.010) 8 14 7 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t ? v ? 14x ref k n n 7.06 14x 0.36 14x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. nlsv4t240e/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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